|
|
|
|
|
|
|
Title
|
System Verilog for verification
|
|
Sub Title
|
a guide to learning the testbench language features
|
|
Author |
|
|
CoAuthor |
|
|
CallNo |
621.392 SPS |
|
Subject |
|
|
ISBN |
9788184895315 |
|
Volume |
|
|
Publisher Name |
Springer (India) Private Limited, |
|
Publishing Year |
2010 |
|
Edition |
2nd
|
|
Pages |
xxxiii,429p
|
|
Price |
0.00 PKR
|
|
Text Language |
English
|
|
Available |
Yes, Accessions:[ 45830 ] |
|
Description |
|
|
Keywords |
|
|
Click Here for MARC 21 View |
|
Catalogue
|
Books
|
|
Periodicals
|
Newspapers
|
Publications
|
|
Research Papers
|
|
|
|
|